A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

被引：67

作者：

Young, KK ^{[1
]}

Wu, SY ^{[1
]}

Wu, CC ^{[1
]}

Wang, CH ^{[1
]}

Lin, CT ^{[1
]}

Cheng, JY ^{[1
]}

Chiang, M ^{[1
]}

Chen, SH ^{[1
]}

Lo, TC ^{[1
]}

Chen, YS ^{[1
]}

Chen, JH ^{[1
]}

Chen, LJ ^{[1
]}

Hou, SY ^{[1
]}

Liaw, JJ ^{[1
]}

Chang, TE ^{[1
]}

Hou, CS ^{[1
]}

Shih, J ^{[1
]}

Jeng, SM ^{[1
]}

Hsieh, HC ^{[1
]}

Ku, Y ^{[1
]}

Yen, T ^{[1
]}

Tao, H ^{[1
]}

Chao, LC ^{[1
]}

Shue, S ^{[1
]}

Jang, SM ^{[1
]}

Ong, TC ^{[1
]}

Yu, CH ^{[1
]}

Liang, MS ^{[1
]}

Diaz, CH ^{[1
]}

Sun, JYC ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co, Hsinchu, Taiwan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A leading-edge 0.13 mum CMOS technology using 193nm lithography and Cu/low-k interconnect is described in this paper. High performance 80nm core devices use 17 Angstrom nitrided oxide for 1.0-1.2V operation. These devices deliver unloaded 8.5ps gate delay @1.2V. This technology also supports general ASIC applications with 20 Angstrom oxide for 1.2-1.5V operation and low-standby power applications with 26 A for 1.5V operation, respectively. Dual gate oxides of 50 or 65 Angstrom are also supported for 2.5V or 3.3V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high-density 1P3M 2.43 mum(2) 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.

引用

页码：563 / 566

页数：4

共 4 条

[1] A 0.15 μm CMOS foundry technology with 0.1 μm devices for high performance applications
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Lee, KW
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[J]. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 146 - 147
[2] DIAZ CH, 1999, TSMC INT MEMO
[3] A modular 0.13 μm bulk CMOS technology for high performance and low power applications
Han, LK
Biesemans, S
Heidenreich, J
Houlihan, K
Lin, C
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Chen, B
[J]. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 12 - 13
[4] A 70 nm gate length CMOS technology with 1.0 V operation
Ono, A
Fukasaku, K
Matsuda, T
Fukai, T
Ikezawa, N
Imai, K
Horiuchi, T
[J]. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 14 - 15

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