A distributed crossbar switch scheduler for on-chip networks

被引：11

作者：

Lee, K ^{[1
]}

Lee, SJ ^{[1
]}

Yoo, HJ ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Semicond Syst Lab, Taejon 305701, South Korea

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249484

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A scheduling algorithm is proposed for lightweight on-chip crossbar switch in on-chip networks. The proposed NA-MOO algorithm distributes the arbitration computing over all of the crossbar fabric nodes. Its implementation shows that it can reduce > 60% area and > 20% computation delay compared to conventional round robin based SLIP algorithm. Its feasibility is analyzed by using a SoC for HDTV as an example. The proposed techniques are area-efficient and show higher performance for the on-chip interconnection networks.

引用

页码：671 / 674

页数：4

共 5 条

[1] Networks on chips: A new SoC paradigm [J].

Benini, L ;

De Micheli, G .

COMPUTER, 2002, 35 (01) :70-+

[2] Designing and implementing a fast crossbar scheduler [J].

Gupta, P ;

McKeown, N .

IEEE MICRO, 1999, 19 (01) :20-28

[3] Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques [J].

Huang, CH ;

Wang, JS ;

Huang, YC .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (01) :63-76

[4]

Lee SJ, 2003, ISSCC DIG TECH PAP I, V46, P468

[5]

YAMAUCHI H, 2002, IEEE ISSCC, P372

← 1 →