Limits of strong phase shift patterning for device research

Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.