Fabrication and testing of vertical metal edge emitters with well defined gate to emitter separation

Vertical metal edge emitter arrays with well defined gate to emitter separations have been fabricated. The emitter to gate spacing is determined by the thickness of a deposited layer which can also serve as a current limiting resistor. Current limiting resistors can also be formed by a self-aligned etch of the underlying substrate. Parts with 300 nm emitter to gate spacing created using a chemical mechanical polishing based process begin to emit at as low as 60 V. While those created using a reactive ion etching process with 200 nm emitter to gate spacing begin to emit at 40 V. Emission stability is good and dc current densities of up to 3 A/cm(2) from 100 emitter arrays on a close packed 5 mu m pitch have been demonstrated. (C) 1996 American Vacuum Society.