Self-aligned μTrench Phase-Change Memory cell architecture for 90nm technology and beyond

被引：13

作者：

Pirovano, A. ^{[1
]}

Pellizzer, F. ^{[1
]}

Tortorelli, I. ^{[1
]}

Harrigan, R. ^{[2
]}

Magistretti, M. ^{[1
]}

Petruzza, P. ^{[1
]}

Varesi, E. ^{[1
]}

Erbetta, D. ^{[1
]}

Marangon, T. ^{[1
]}

Bedeschi, F. ^{[1
]}

Fackenthal, R. ^{[2
]}

Atwood, G. ^{[2
]}

Bez, R. ^{[1
]}

机构：

[1] STMicroelect, NVMTD, FMG, Via C Olivetti 2, I-20041 Agrate Brianza, Italy

[2] Intel Corp, Santa Clara, CA USA

来源：

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2007年

关键词：

D O I：

10.1109/ESSDERC.2007.4430918

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel self-aligned mu Trench-based cell architecture for Phase Change Memory (PCM) process is presented. The low-programming current and the good dimensional control of the sub-lithographic features achieved with the mu Trench structure are combined with a self-aligned patterning strategy that simplify the integration process in term of alignment tolerances and of number of critical masks. The proposed architecture has been integrated in a 90nm 128Mb vehicle with programming currents of 300 mu A and good distributions, demonstrating its suitability for the production of high-density PCM arrays at 90nm and beyond.

引用

页码：222 / +

页数：2

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