67-GHz static frequency divider using 0.2-μm self-aligned SiGeHBTs

被引:19
作者
Washio, K [1 ]
Hayami, R
Ohue, E
Oda, K
Tanabe, M
Shimamoto, H
Kondo, M
机构
[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan
[2] Hitachi Device Engn Corp Ltd, Musashino Off, Kokubunji, Tokyo 1858601, Japan
关键词
bipolar transistors; emitter coupled logic; epitaxial growth; frequency conversion; heterojunctions; millimeter-wave bipolar integrated circuits; MIMICs; optical communication;
D O I
10.1109/22.899955
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 67-GHz 1/4 static frequency divider using 0.2-mum self-aligned selective-epitaxial-growth SiGe heterojunction bipolar transistors, with a 122-GHz cutoff frequency, a 163-GHz maximum oscillation frequency, and an average emitter coupled logic gate delay time of 5.65 ps, was developed. The pretracking master-slave toggle flip-flop OMS-TFF) of the divider increases the maximum operating frequency to about 15% higher than that of a conventional MS-TFF, yet the power consumption of the divider is 175 mW, which is 1/5 that of comparable dividers, at a supply voltage of -5.2 V.
引用
收藏
页码:3 / 8
页数:6
相关论文
共 10 条
[1]   A 0.2-μm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors [J].
Hashimoto, T ;
Kikuchi, T ;
Watanabe, K ;
Ohashi, N ;
Saito, T ;
Yamaguchi, H ;
Wada, S ;
Natsuaki, N ;
Kondo, M ;
Kondo, S ;
Homma, Y ;
Owada, N ;
Ikeda, T .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :209-212
[2]  
LEE Q, 1999, IEEE RFIC S JUN
[3]  
Nakajima H., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P771, DOI 10.1109/IEDM.1999.824264
[4]   130-GHz fT SiGe HBT technology [J].
Oda, K ;
Ohue, E ;
Tanabe, M ;
Shimamoto, H ;
Onai, T ;
Washio, K .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :791-794
[5]   A 7.7-ps CML using selective-epitaxial SiGe HBTs [J].
Ohue, E ;
Oda, K ;
Hayami, R ;
Washio, K .
PROCEEDINGS OF THE 1998 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 1998, :97-100
[6]   AN 8-BIT 250 MEGASAMPLE PER 2ND ANALOG-TO-DIGITAL CONVERTER - OPERATION WITHOUT A SAMPLE AND HOLD [J].
PEETZ, B ;
HAMILTON, BD ;
KANG, J .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (06) :997-1002
[7]  
Washburn S, 1999, MENOPAUSE, V6, P7
[8]   A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-gate delay [J].
Washio, K ;
Ohue, E ;
Oda, K ;
Tanabe, M ;
Shimamoto, H ;
Onai, T .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :795-798
[9]  
WASHIO K, 1998, ISSCC, P312
[10]  
WASHIO K, 2000, ISSCC, P210