On the simulation of fast settling charge pump PLLs up to fourth order

被引:9
作者
Guermandi, Marco [1 ]
Franchi, Eleonora [1 ]
Gnudi, Antonio [1 ]
机构
[1] Univ Bologna, ARCES, I-40136 Bologna, Italy
关键词
phase-locked loop (PLL); time-domain model; z-domain model; phase noise; reference spurs; ultra-wide band (UWB); N FREQUENCY-SYNTHESIZERS; PHASE NOISE; CMOS PLL; TIME; LOOPS; MODEL;
D O I
10.1002/cta.700
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we discuss three different models for the simulation of integer-N charge-pump phase-locked loops (PLLs), namely the continuous-time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time-domain model are introduced and the results are compared with those obtained by means of the s-domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems. Copyright (C) 2010 John Wiley & Sons, Ltd.
引用
收藏
页码:1257 / 1273
页数:17
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