Processor-based built-in self-test for embedded DRAM

A built-in self-test engine and test methodology have been del eloped for testing a family of high-bandwidth, high-density DRAM micros. The DRAM macros [1] range in size from 256 x 16 x 128 to 2 K x: 16 x 256 (Word x Bit x Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM highperformance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is architected for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations.