Parallel squarer using Booth-folding technique

被引：18

作者：

De Caro, D ^{[1
]}

Strollo, AGM ^{[1
]}

机构：

[1] Univ Naples Federico II, Dept Elect & Telecommun Engn, I-80125 Naples, Italy

来源：

ELECTRONICS LETTERS | 2001年 / 37卷 / 06期

关键词：

D O I：

10.1049/el:20010241

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new technique is presented for designing a parallel squarer that uses both the Booth-encoding and the 'traditional' folding technique. The proposed Booth-folding technique achieves a 50% reduction in the number of partial products with respect to the simple folding architecture. enabling the propagation delay and power dissipation to be significantly reduced.

引用

页码：346 / 347

页数：2

共 5 条

[1] An Integrated Circuit Design for Pruned Tree-Search Vector Quantization Encoding with an Off-Chip Controller [J].