Stability of pentacene top gated thin film transistors

被引:33
作者
Diallo, K.
Erouel, M.
Tardy, J.
Andre, E.
Garden, J.-L.
机构
[1] Ecole Cent Lyon, Lyon Inst Nanotechnol, CNRS, UMR 5270, F-69134 Ecully, France
[2] CNRS, Inst Neel, F-38042 Grenoble, France
[3] Univ Grenoble 1, F-38042 Grenoble, France
关键词
D O I
10.1063/1.2802039
中图分类号
O59 [应用物理学];
学科分类号
摘要
We report on the stability of top gated pentacene field effect transistors processed on Kapton (TM) with Parylene-C as gate dielectric. The influence of bias stress and ambient atmosphere on device characteristics were investigated. Combined influence of moisture and gate bias stress led to an increase of depletion current and subthreshold slope as well as a drift of onset voltage and threshold voltage. We show that devices stressed in the off state exhibit a high stability. (C) 2007 American Institute of Physics.
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页数:3
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