45-nm gate length CMOS technology and beyond using steep halo

被引：42

作者：

Wakabayashi, H ^{[1
]}

Ueki, M ^{[1
]}

Narihiro, M ^{[1
]}

Fukai, T ^{[1
]}

Ikezawa, N ^{[1
]}

Matsuda, T ^{[1
]}

Yoshida, K ^{[1
]}

Takeuchi, K ^{[1
]}

Ochiai, Y ^{[1
]}

Mogami, T ^{[1
]}

Kunio, T ^{[1
]}

机构：

[1] NEC Corp Ltd, Syst Devices & Fundamental Res, Sagamihara, Kanagawa 2290098, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904256

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 muA/mum for an off current less than 10 nA/mum at 1.2 V. For an off current less than 300 nA/mum, 33-nm pMOSFETs have a high drive current of 403 muA/mum at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 muA/mum for an off current less than 300 nA/mum at 1.2 V.

引用

页码：49 / 52

页数：4

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