Write current reduction in transition metal oxide based resistance-change memory

被引:149
作者
Ahn, Seung-Eon
Lee, Myoung-Jae [1 ]
Park, Youngsoo [1 ]
Kang, Bo Soo [1 ]
Lee, Chang Bum [1 ]
Kim, Ki Hwan [1 ]
Seo, Sunae
Suh, Dong-Seok
Kim, Dong-Chirl [1 ]
Hur, Jihyun [1 ,2 ]
Xianyu, Wenxu [1 ]
Stefanovich, Genrikh [1 ]
Yin, Hit. Axiang [1 ]
Yoo, In-Kyeong [1 ]
Lee, Atng-Hyun
Park, Jong-Bong [3 ]
Baek, In-Gyu [4 ]
Park, Bae Ho [5 ]
机构
[1] Samsung Adv Inst Technol, Semicond Design Lab, Suwon 440600, South Korea
[2] Samsung Adv Inst Technol, Nano Fabricat Technol Ctr, Suwon 440600, South Korea
[3] Samsung Adv Inst Technol, Analyt Engn Ctr, Suwon 440600, South Korea
[4] Samsung Adv Inst Technol, Adv Proc Dev Team, Semicond R&D Ctr, Suwon 440600, South Korea
[5] Konkuk Univ, Dept Phys, Seoul 143701, South Korea
关键词
D O I
10.1002/adma.200702081
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
A novel memory cell structure with a Pt/Ti-doped NiO/Pt architecture is shown to exhibit the lowest write current reported thus far for a unipolar switching resistance-change-based device, as shown in the figure. The write current decreases dramatically upon scaling to cell sizes smaller than 100 nm x 100 nm. High-density universal memory can be fabricated by combining this node element with a selective switch.
引用
收藏
页码:924 / +
页数:6
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