Properties of high-voltage stress generated traps in thin silicon oxide

被引:42
作者
Scott, RS
Dumin, NA
Hughes, TW
Dumin, DJ
Moore, BT
机构
[1] CLEMSON UNIV,DEPT ELECT & COMP ENGN,CTR SEMICOND DEVICE RELIABIL RES,CLEMSON,SC 29634
[2] ADV MICRO DEVICES INC,AUSTIN,TX 78741
关键词
D O I
10.1109/16.502425
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
It has previously been shown that trap generation inside thin oxides during high voltage stressing can be coupled to time-dependent-dielectric-breakdown distributions through the statistics linking wearout to breakdown. Since the stress-generated traps play a crucial role in the wearout/breakdown process, it is important to understand the properties of these traps. The properties of the traps in oxides with thicknesses between 2.5 nm and 22 nm have been studied, with emphasis on oxides in the 8.5-nm to 13-nm thickness range. The Coulombic scattering cross section of the traps responsible for the reduction in the tunneling current, an estimate of the spatial and energy distribution of the traps, and the charging/discharging properties of the traps have been measured. It will be shown that the measured properties of the high-voltage, stress-generated traps can be adequately described by the tunneling of electrons into and out of traps.
引用
收藏
页码:1133 / 1143
页数:11
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