Variance reduction using wafer patterns in IddQ data

被引：64

作者：

Daasch, WR ^{[1
]}

McNames, J ^{[1
]}

Bockelman, D ^{[1
]}

Cota, K ^{[1
]}

Madge, R ^{[1
]}

机构：

[1] Portland State Univ, IC Design & Test Lab, Portland, OR 97207 USA

来源：

INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/TEST.2000.894206

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The subject of this paper is I-ddQ testing for deep submicron CMOS technologies. The key concept introduced is the need to reduce the variance of good and faulty I-ddQ distributions. Other I-ddQ based techniques are reviewed within the context of variance reduction. Using the SEMATECH data and production data, variance reduction techniques are demonstrated. The main contribution of the paper is the systematic use of the die location and patterns in the I-ddQ data to reduce variance. Variance reduction is completed before any I-ddQ threshold limits are set.

引用

页码：189 / 198

页数：10

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