Fabrication method for IC-oriented Si twin-island single-electron transistors

被引：6

作者：

Ono, Y ^{[1
]}

Takahashi, Y ^{[1
]}

Yamazaki, K ^{[1
]}

Nagase, M ^{[1
]}

Namatsu, H ^{[1
]}

Kurihara, K ^{[1
]}

Murase, K ^{[1
]}

机构：

[1] Nippon Telegraph & Tel Corp, Basic Res Labs, Atsugi, Kanagawa 2430198, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746294

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method enables us to fabricate, in a self-aligned way, a twin-island SET in which two Si islands are aligned in parallel. Experimental devices demonstrated, at 40 K, that the twin-island SET structure can be operated as two individual SETs. Since the two SETs are packed in a tiny area, this method is suitable for constructing logic circuits based on pass-transistor-type logic and CMOS-type logic, which promises to lead to single-electron logic LSIs.

引用

页码：123 / 126

页数：4

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