30nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

Planar CMOS: transistors have been fabricated to evaluate the 70nm technology node using conventional transistor design methodologies. Conventional CMOS transistors with 30nm physical gate length were fabricated using aggressively scaled junctions, polysilicon gate electrode, gate oxide and Ni silicide. These devices have inversion Cox exceeding 1.9 muF/cm2, n-MOS gate delay (CV/I) of 0.94 ps and p-MOS gate delay of 1.7 ps at V-cc=0.85V. These are the smallest CV/I values ever reported for Si CMOS devices. The transistors also show good short channel control and subthreshold swings. The n-MOS and p-MOS have drive currents equal to 514 muA/mum and 285 muA/mum respectively with I-off at or below 100nA/mum at Vcc=0.85V. The saturation gm is equal to 1200mS/mm for n-MOS and 640mS/mm for p-MOS. These are among the highest gm values ever reported. The junction edge leakage is reasonably low with less than 1nA/um at 1.0V and 100C for both n-MOS and p-MOS. These encouraging results suggest that the 70nm technology node is achievable using conventional planar transistor design and process flow.