Combinatorial fabrication process for a-Si:H thin film transistors

被引：8

作者：

Aiyer, HN

Nishioka, D

Maruyama, R

Shinno, H

Matsuki, N

Miyazaki, K

Fujioka, H

Koinuma, H

机构：

[1] Tokyo Inst Technol, Ceram Mat & Struct Lab, Midori Ku, Yokohama, Kanagawa 2268503, Japan

[2] Univ Tokyo, Dept Appl Chem, Bunkyo Ku, Tokyo 1138656, Japan

[3] Waseda Univ, CREST, Japan Sci & Technol Corp, Shinjuku Ku, Tokyo 1690072, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS | 2001年 / 40卷 / 1AB期

关键词：

plasma enhanced chemical vapor deposition; hydrogenated amorphous silicon; thin film transistor;

D O I：

10.1143/JJAP.40.L81

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A combinatorial approach is proposed and demonstrated for the parallel fabrication of a-Si:H, alloy and a-Si:H based devices, by employing simple masking schemes in conventional plasma-enhanced chemical vapor deposition (PECVD). The results are presented for a-Si:H thin film transistors. A (7 x 7) combinatorial device library was deposited on a (indium tin oxide/glass) substrate with the thicknesses of a-SiN:H and a-Si:H as combinatorial variables along the X and Y axes, respectively. Different a-Si:H TFTs in the library were evaluated to yield electrical performance with on-to-off current ratios exceeding 10(4) and threshold voltages from 0.3 to 4.5 V. Combinatorial PECVD offers an efficient and low cost means of studying the a-Si:H device performance and optimization.

引用

页码：L81 / L83

页数：3