DC Voltage Controller for Asymmetric-Twin-Converter-Topology-Based High-Power STATCOM

被引:32
作者
Anand, Sandeep [1 ]
Fernandes, B. G. [1 ]
Chatterjee, Kishore [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India
关键词
DC voltage regulation; harmonic suppression; multilevel operation; pulsewidth modulation (PWM); static compensator (STATCOM); CASCADED MULTILEVEL CONVERTERS; INDUSTRIAL APPLICATIONS; INVERTERS; MODULATION; REQUIREMENTS; STRATEGY;
D O I
10.1109/TIE.2012.2185023
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A four-level static compensator integrating two 2-level converters, supplying/absorbing reactive power to/from the grid, is reported in our earlier paper. Reduced component count, simpler layout for switches, and smaller dc-link capacitor values are the attractive features of the proposed topology over the diode clamped and cascaded multilevel converters. This paper suggests further improvements in this topology. Suitable selection of the dc-link voltage values reduces distortion in the current fed to the grid. In addition, circuit topology is modified to avoid the split-capacitor dc links. This reduces the number of independent dc capacitor voltages to be controlled and eliminates the flow of third-harmonic current through the transformer. In order to improve the performance, a phase-shifted carrier-based pulsewidth modulation technique is used. A mathematical model of the system is derived, based on which a controller for the scheme is designed. The effectiveness of the scheme is verified through detailed simulation study. To confirm the viability of the scheme, experimental studies are carried out on a scaled-down laboratory prototype developed for the purpose.
引用
收藏
页码:11 / 19
页数:9
相关论文
共 27 条
[11]   Recent Advances and Industrial Applications of Multilevel Converters [J].
Kouro, Samir ;
Malinowski, Mariusz ;
Gopakumar, K. ;
Pou, Josep ;
Franquelo, Leopoldo G. ;
Wu, Bin ;
Rodriguez, Jose ;
Perez, Marcelo A. ;
Leon, Jose I. .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2010, 57 (08) :2553-2580
[12]   A 31-level cascade inverter for power applications [J].
Lee, CK ;
Hui, SYR ;
Chung, HSH .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2002, 49 (03) :613-617
[13]   Unidimensional Modulation Technique for Cascaded Multilevel Converters [J].
Leon, Jose I. ;
Vazquez, Sergio ;
Kouro, Samir ;
Franquelo, Leopoldo G. ;
Carrasco, Juan M. ;
Rodriguez, Jose .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2009, 56 (08) :2981-2986
[14]   Small-Signal Model-Based Control Strategy for Balancing Individual DC Capacitor Voltages in Cascade Multilevel Inverter-Based STATCOM [J].
Liu, Yu ;
Huang, Alex Q. ;
Song, Wenchao ;
Bhattacharya, Subhashish ;
Tan, Guojun .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2009, 56 (06) :2259-2269
[15]   Asymmetrical Cascade Multilevel Converters With Noninteger or Dynamically Changing DC Voltage Ratios: Concepts and Modulation Techniques [J].
Lu, Shuai ;
Mariethoz, Sebastien ;
Corzine, Keith A. .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2010, 57 (07) :2411-2418
[16]   A Survey on Cascaded Multilevel Inverters [J].
Malinowski, Mariusz ;
Gopakumar, K. ;
Rodriguez, Jose ;
Perez, Marcelo A. .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2010, 57 (07) :2197-2206
[17]   Multicarrier PWM strategies for multilevel inverters [J].
McGrath, BP ;
Holmes, DG .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2002, 49 (04) :858-867
[18]   A harmonic elimination and suppression scheme for an open-end winding induction motor drive [J].
Mohapatra, KK ;
Gopakumar, K ;
Somasekhar, VT ;
Umanand, L .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2003, 50 (06) :1187-1198
[19]   Distribution system compensation using a new binary multilevel voltage source inverter [J].
Patil, KV ;
Mathur, RM ;
Jiang, J ;
Hosseini, SH .
IEEE TRANSACTIONS ON POWER DELIVERY, 1999, 14 (02) :459-464
[20]  
Peng FZ, 1998, IEEE T IND APPL, V34, P1293, DOI 10.1109/28.739012