Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65nm-node high performance eDRAM

被引：33

作者：

Kajita, A ^{[1
]}

Usui, T ^{[1
]}

Yamada, M ^{[1
]}

Ogawa, E ^{[1
]}

Katata, T ^{[1
]}

Sakata, A ^{[1
]}

Miyajima, H ^{[1
]}

Kojima, A ^{[1
]}

Kanamura, R ^{[1
]}

Ohoka, Y ^{[1
]}

Kawashima, H ^{[1
]}

Tabuchi, K ^{[1
]}

Nagahata, K ^{[1
]}

Kato, Y ^{[1
]}

Hayashi, T ^{[1
]}

Kadomura, S ^{[1
]}

Shibata, H ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, SoC Res & Dev Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2003年

关键词：

D O I：

10.1109/IITC.2003.1219697

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

100nm half-pitch Cu dual-damascene (DD) interconnects with low-k hybrid (PAE(k2.65)/SiOC(k2.5)/SiC(k3.5)) dielectrics have been successfully integrated for a 65nm-node high performance embedded DRAM. The hybrid-DD structure was fabricated by applying a hard mask process combined with Stacked Mask Process (S-MAP). Well-controlled DD profile of the hybrid structure can provide the advantage of void-less Cu fill, resulting from over-hang reduction of PVD barrier metal. Stress-induced voiding (SiV), which is becoming a more serious problem with down scaling of via-hole dimension was found to be drastically improved as compared with homogeneous-DD structures. Thermal cycle test (TCT) also shows no degradation of the wiring/via-hole properties. Moreover, the result of electromigration (EM) test shows a tight distribution of mean time to failure (MTF). The hybrid-DD structure can extend the PVD Cu filling process to 65nm-node Cu metallization with excellent reliability.

引用

页码：9 / 11

页数：3

共 4 条

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