A double-level-V-th select gate array architecture for multilevel NAND flash memories

In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely, This paper describes how in a conventional NAND hash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider, This paper describes a new array architecture, ''A double-level-V-th, select gate array architecture'' to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line, The threshold voltage fluctuation can be as much as 0.7 V in a conventional array, in the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines, Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed, The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized.