0.2-μm fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-mu m, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C-f(ext)) of conventional Y-shaped gate HJFET's, The 0.2-mu m Y-shaped gate openings are realized by anisotoropic dry-etching with stepper lithography and SiO2 sidewall techniques instead of electron beam lithography, By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0,2-mu m gate n-Al0.2Ga0.8As/In0.2Ga0.8As HJFET shows very small current saturation voltage of 0.25 V, marked gm(max) Of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV, Also, the improved rf-performance such as f(T) = 71 GBz and f(max) = 120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C-f(ext). The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's.