Modeling of direct tunneling and surface roughness effects on C-V characteristics of ultra-thin gate MOS capacitors

被引:21
作者
Zhang, JL
Yuan, JS [1 ]
Ma, Y
Oates, AS
机构
[1] Univ Cent Florida, Coll Engn, Dept Elect & Comp Engn,Chip Design & Reliabil Lab, Sch Elect Engn & Comp Sci, Orlando, FL 32816 USA
[2] Lucent Technol, Bell Labs, Orlando, FL 32819 USA
关键词
D O I
10.1016/S0038-1101(00)00234-3
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Effects of direct tunneling and surface roughness on the capacitance-voltage characteristics of ultra-thin gate deep submicron MOS transistors have been studied. An improved equivalent circuit model to account for surface roughness and direct tunneling on the ultra-thin gate MOS capacitors in a unified manner is proposed. The capacitance subject to direct tunneling and surface roughness effect is smaller than that without surface roughness effect. (C) 2001 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:373 / 377
页数:5
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