Fabrication of gate-all-around transistors using metal induced lateral crystallization

被引：8

作者：

Chan, VWC ^{[1
]}

Chan, PCH ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect, Kowloon, Hong Kong, Peoples R China

来源：

IEEE ELECTRON DEVICE LETTERS | 2001年 / 22卷 / 02期

关键词：

double gate transistors; gate-all-around transistors; metal induced lateral crystallization; SOI; thin-film transistors;

D O I：

10.1109/55.902838

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Gate-all-around transistor (GAT) is demonstrated. The device can be fabricated on either a bulk silicon wafer or on the top of any device layers. The fabrication process used a new technique called metal-induced-lateral-crystallization (MILC) to recrystallize the amorphous silicon to form large silicon grain in the active area. Using this technique, the transistor performance is comparable to a SOI MOSFET. Compared with the single-gate thin film transistor (SGT) and solid phase crystallization (SPC) device, MILC GAT has lower subthreshold slope, lon er threshold voltage, higher transconductance and nearly double drive current. The impact of short channel length was investigated.

引用

页码：80 / 82

页数：3

共 11 条

[1]

Colinge J. P., 1990, International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4), P595, DOI 10.1109/IEDM.1990.237128

[2] A C-switch cell for low-voltage and high-density SRAM's [J].

Kuriyama, H ;

Ishigaki, Y ;

Fujii, Y ;

Maegawa, S ;

Maeda, S ;

Miyamoto, S ;

Tsutsumi, K ;

Miyoshi, H ;

Yasuoka, A .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (12) :2483-2488

[3]

LEE JH, 1999, IEDM, P71

[4] High performance low temperature metal-induced unilaterally crystallized polycrystalline silicon thin film transistors for system-on-panel applications [J].

Meng, ZG ;

Wang, MX ;

Wong, M .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (02) :404-409

[5] Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's [J].

Miyamoto, S ;

Maegawa, S ;

Maeda, S ;

Ipposhi, T ;

Kuriyama, H ;

Nishimura, T ;

Tsubouchi, N .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (08) :1693-1698

[6]

PAE S, 1999, P IEEE SOI C OCT, P108

[7]

TANAKA T, 1994, S VLSI TECHN, P11

[8] Super thin-film transistor with SOICMOS performance formed by a novel grain enhancement method [J].

Wang, HM ;

Chan, MS ;

Jagar, S ;

Poon, VMC ;

Qin, M ;

Wang, YY ;

Ko, PK .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (08) :1580-1586

[9] The behavior of narrow-width SOI MOSFET's with MESA isolation [J].

Wang, HM ;

Chan, MS ;

Wang, YY ;

Ko, PK .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (03) :593-600

[10] Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel [J].

Wong, HSP ;

Chan, KK ;

Taur, Y .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :427-430

← 1 2 →