Fabrication of self-aligned 90-nm fully depleted SOICMOS SLOTFETs

被引：7

作者：

Chen, CK ^{[1
]}

Chen, CL ^{[1
]}

Gouker, PM ^{[1
]}

Wyatt, PW ^{[1
]}

Yost, DR ^{[1
]}

Burns, JA ^{[1
]}

Suntharalingam, V ^{[1
]}

Fritze, M ^{[1
]}

Keast, CL ^{[1
]}

机构：

[1] MIT, Lincoln Lab, Lexington, MA 02420 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2001年 / 22卷 / 07期

关键词：

CMOS; MOSFETs; SOI technology;

D O I：

10.1109/55.930686

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate. Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured.

引用

页码：345 / 347

页数：3

共 5 条

[1] RECESSED-CHANNEL STRUCTURE FOR FABRICATING ULTRATHIN SOI MOSFET WITH LOW SERIES RESISTANCE [J].