Impact of crosstalk on delay time and a hierarchy of interconnects

被引：8

作者：

Yamashita, K ^{[1
]}

Odanaka, S ^{[1
]}

机构：

[1] Matsushita Elect Corp, ULSI Proc Technol Dev Ctr, Minami Ku, Kyoto 601, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746357

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Impact of crosstalk on delay time and a hierarchy of interconnects is clarified. The delay time increase is induced by the almost same phenomenon as the crosstalk noise in short interconnects. For global interconnects, the delay time increase by crosstalk is enhanced and hence the delay time improvement trades off between the reduction of the lateral capacitance and the increase of wiring resistance. A multilevel interconnect scheme at each technology generation is further investigated considering the crosstalk effect. Delay time improvements by circuit techniques are discussed to reduce the delay time increase by crosstalk.

引用

页码：291 / 294

页数：4

共 7 条

[1]

Alpert CJ, 1998, 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, P362, DOI 10.1109/DAC.1998.724498

[2] Interconnect capacitance, crosstalk, and signal delay for 0.35 mu m CMOS technology [J].

Cho, DH ;

Eo, YS ;

Seung, MH ;

Kim, NH ;

Wee, JK ;

Kwon, OK ;

Park, HS .

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :619-622

[3]

Rahmat K, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P245, DOI 10.1109/IEDM.1995.499188

[4] CLOSED-FORM EXPRESSIONS FOR INTERCONNECTION DELAY, COUPLING, AND CROSSTALK IN VLSIS [J].

SAKURAI, T .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (01) :118-124

[5]

*SEM IND ASS, 1997, WORKSH WORK GROUP RE

[6]

SYLVESTER D, 1998, S VLSI TECHN, P42

[7]

Yamashita K, 1997, 1997 SYMPOSIUM ON VLSI TECHNOLOGY, P53, DOI 10.1109/VLSIT.1997.623691

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