Optimisation of channel thickness in strained Si/SiGe MOSFETs

被引：13

作者：

Kwa, KSK ^{[1
]}

Chattopadhyay, S ^{[1
]}

Olsen, SH ^{[1
]}

Driscoll, LS ^{[1
]}

O'Neill, AG ^{[1
]}

机构：

[1] Univ Newcastle Upon Tyne, Sch Elect Elect & Comp Engn, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England

来源：

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSDERC.2003.1256923

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

It is demonstrated from experimental I-V and C-V data, and confirmed by computer simulation, that strained Si/SiGe MOSFET performance severely degrades below a channel thickness of 7 nm. MOSFETs with strained Si channels of thickness 5 nm, 7 nm and 9 nm have been fabricated using a conventional high thermal budget process. The performance degradation is attributed to Ge diffusion through the strained Si layer, which causes a build lip of gate oxide charge.

引用

页码：501 / 504

页数：4

共 9 条

[1] Thermal stability of undoped strained Si channel SiGe heterostructures [J].