Low temperature crystallized Ta2O5/Nb2O5 bi-layers integrated into RIR capacitor for 60 nm generation and beyond

被引：18

作者：

Cho, KH ^{[1
]}

Lee, J ^{[1
]}

Lim, JS ^{[1
]}

Lim, H ^{[1
]}

Lee, J ^{[1
]}

Park, S ^{[1
]}

Yoo, CY ^{[1
]}

Kim, ST ^{[1
]}

Chung, UI ^{[1
]}

Moon, JT ^{[1
]}

机构：

[1] Samsung Elect Co, Proc Dev Team, Semicond R&D Ctr, Yongin 449711, Gyeonggi, South Korea

来源：

MICROELECTRONIC ENGINEERING | 2005年 / 80卷

关键词：

Ta2O5/Nb2O5; DRAM capacitor; RIR;

D O I：

10.1016/j.mee.2005.04.032

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ta2O5/Nb2O5 bi-layers were prepared on Ru/SiO2/Si substrate by Atomic Layer Deposition, and post annealed up to 575 degrees C. The crystallization temperature of the bi-layers was 550 degrees C, which was 100 degrees C lower than that of Ta2O5 single layer. The thickness of the dielectric layers was also important parameter for the crystallization temperature. Transmittance Electron Microscopy image and depth profile analysis showed that Ta2O5 and Nb2O5 mixed each other during the crystallization. It was suggested that inter diffusion of two layers decreased the crystallization temperature of the bi-layers. Equivalent oxide thickness of crystalline Ru/Ta2O5/Nb2O5/Ru capacitor was 7.6 angstrom with less than 100 nA/cm(2) leakage currents, which satisfied the requirements for 60 nm generation DRAM capacitor and beyond.

引用

页码：317 / 320

页数：4

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