A Faraday cage isolation structure for substrate crosstalk suppression

被引:40
作者
Wu, JH
Scholvin, J
del Alamo, JA
Jenkins, KA
机构
[1] MIT, Cambridge, MA 02139 USA
[2] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
关键词
isolation technology; mixed-signal circuits; RF circuits; substrate crosstalk; system-on-a-chip;
D O I
10.1109/7260.959312
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have exploited a recently-developed, through-wafer via technology in silicon to implement a novel Faraday cage scheme for substrate crosstalk suppression in system-on-chip (SOC) applications. The Faraday cage structure consists of a ring of grounded vias encircling sensitive or noisy portions of a chip. The via technology features high aspect ratio, through-wafer holes filled with electroplated Cu and lined with a silicon nitride barrier layer. The new Faraday cage structure has shown crosstalk suppression of 40 dB at 1 GHz and 36 dB at 5 GHz at a distance of 100 mum. This is about 10 dB better than any other isolation technique previously reported.
引用
收藏
页码:410 / 412
页数:3
相关论文
共 12 条
[1]   Characterization of a time multiplexed inductively coupled plasma etcher [J].
Ayón, AA ;
Braff, R ;
Lin, CC ;
Sawin, HH ;
Schmidt, MA .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1999, 146 (01) :339-349
[2]   COMPARISON OF SOI AND JUNCTION ISOLATION FOR SUBSTRATE CROSSTALK SUPPRESSION IN MIXED-MODE INTEGRATED-CIRCUITS [J].
JOARDAR, K .
ELECTRONICS LETTERS, 1995, 31 (15) :1230-1231
[3]  
JOARDAR K, 1995, BIP BICMOS CIRC TECH, P178
[4]   Suppression of substrate crosstalk in mixed-signal complementary MOS circuits using high-resistivity SIMOX (Separation by IMplanted OXygen) wafers [J].
Kodate, J ;
Harada, M ;
Tsukahara, T .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2000, 39 (4B) :2256-2260
[5]  
MERRILL RB, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P433, DOI 10.1109/IEDM.1994.383375
[6]   A micromachining post-process module for RF silicon technology [J].
Pham, NP ;
Ng, KT ;
Bartek, M ;
Sarro, PM ;
Rejaei, B ;
Burghartz, JN .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :481-484
[7]  
RAHIM I, 1992, IEE INT SOI C, P170
[8]   Substrate crosstalk reduction using SOI technology [J].
Raskin, JP ;
Viviani, A ;
Flandre, D ;
Colinge, JP .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (12) :2252-2261
[9]   EXPERIMENTAL RESULTS AND MODELING TECHNIQUES FOR SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED-CIRCUITS [J].
SU, DK ;
LOINAZ, MJ ;
MASUI, S ;
WOOLEY, BA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (04) :420-430
[10]  
Viviani A, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P713, DOI 10.1109/IEDM.1995.499318