Examination of the time power law dependencies in hot carrier stressing of n-MOS transistors

The origins of the different power laws arising from hot carrier stressing at low and high gate voltages are examined. It is found that damage at V-g = V-d (predominantly electron trapping in the oxide) has the same underlying 0.5 power law exponent dependence as stress under I-b(max) (interface state creation) conditions, if degradation is measured as a function of injected electronic charge instead of time. It is proposed that the reduced gradient normally seen under V-g = V-d stresses arises due to the repulsive electrostatic oxide fields created by the trapped oxide charge and does not reflect the fundamental rate of trap creation. Stressing at low gate voltages (V-g = V-d/5) also reveals the presence of a similar time power law of exponent 0.5 when the oxide trap contribution alone is separated out from the rest of the damage. It is concluded that the 0.5 power law appears to be the fundamental underlying kinetic equation that is seen throughout the gate voltage stress range, despite the different types of damage and the very different trap creation mechanisms.