Analog circuit sizing using local biasing

The analog circuit design approach based on local biasing is shown to be very attractive as it removes the nonlinearity in the biasing procedure. Based on this design approach, we offer a new technique for the sizing of analog integrated circuits. The proposed technique is based on the relations that exist between linear elements of a cut-set or a loop when the voltages and currents in the remaining elements are held fixed. These relations enable the designer to fix a circuit variable (biasing current or voltage of a transistor) in exchange for a set of interrelated element values that can be independently changed. The proposed procedure allows us to directly change the element values or the DC parameter values for the active loads without being concerned about the DC biasing. Therefore, the circuit designer is able to manage tradeoffs in the design by comparing multiple solutions that meet the desired criteria. Moreover, multiple circuit simulations are not necessary in the case when any of the calculated element values is not realistic or workable.