Effects of conductivity of polysilicon on profile distortion

The profile distortion, notch, in the etching of gate lines with high-density plasmas is becoming more deleterious as ULSI devices are being further scaled down. Dependence of the etch profiles on the polysilicon conductivity was studied for various spacings of line-and-space patterns. The notch depth was deeper for polysilicon with higher conductivity. The image potential was employed to account for the dependence of notch on conductivity. To measure the net positive charges which are known to contribute to the notch phenomenon, we observed the ion and electron current waveforms from patterned and unpatterned wafers as a function of bias power. The results showed that the surface of the patterned wafer is more positively charged than that of the unpatterned wafer, and the net charge can be reduced by raising the bias power. However, an increase in the bias power lowers the selectivities over both thin gate oxide and photoresist.