A compact physical via blockage model

被引：15

作者：

Chen, Q ^{[1
]}

Davis, JA

Zarkesh-Ha, P

Meindl, JD

机构：

[1] Georgia Inst Technol, Ctr Microelect Res, Atlanta, GA 30332 USA

[2] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2000年 / 8卷 / 06期

关键词：

analysis; channel-routing; design; SLIP99 : system level interconnect; system-level; via blockage;

D O I：

10.1109/92.902263

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Via blockage due to signal interconnects and its impact on wirability of multi-billion-transistor chips are systematically analyzed. Via classifications are introduced. By taking advantage of a stochastic interconnect length distribution and a multi-level interconnect network architecture, a physical via blockage model exploiting channel availability is proposed, This model reveals that the most severe via blockage occurs on first metal level, wasting more than 10% and up to about 50% of wiring area. A new perspective on chip size limit imposed by via blockage is also provided by using the proposed model.

引用

页码：689 / 692

页数：4

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