3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f(MAX) (338 GHz) and a low f(T) (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f(T) and f(MAX), a simple figure of merit proportional to rootf(T)/RBCCB with R-B and C-CB extracted from S-parameter measurement is best correlated to the minimum gate delay.