GAARP: A power-aware GALS architecture for real-time algorithm-specific tasks

被引:7
作者
Bhunia, S [1 ]
Datta, A [1 ]
Banerjee, N [1 ]
Roy, K [1 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47906 USA
关键词
asynchronous/synchronous operations; algorithms implemented in hardware; fault tolerance; energy-aware systems;
D O I
10.1109/TC.2005.99
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Reducing the energy consumption of a real-time system has emerged as an important design concern. In this paper, we propose GAARP, an adaptive scalable architecture targeted toward algorithm-specific tasks for just-in-time performance using the right amount of power. The architecture consists of Globally Asynchronous and Locally Synchronous ( GALS) building blocks, where the processing hardware is realized by a set of smaller slices of similar structure, each running synchronously with independent clocks. We demonstrate that, for different real-time commercial applications with algorithm-specific jobs like online transaction processing, digital filtering, Fourier transform, etc., the proposed architecture allows dynamic load-balancing and adaptive intertask voltage scaling based on the load in each of the processing units. Compared to a synchronous implementation of the same functionality, we show that the proposed hardware can achieve higher efficiency in terms of power and performance by exploiting the flexibility to balance the load and change the supply voltage. The architecture also lends itself to process tolerance since it can detect process-shifts for the individual processing units and determine the appropriate operating voltage/frequency for each unit. Simulation results for two representative applications show that, for a modest system configuration and random job distribution, we obtain up to 67 percent improvement in MOPS/W ( millions of operations per second per watt) over a fully synchronous implementation.
引用
收藏
页码:752 / 766
页数:15
相关论文
共 32 条
[1]   Power-aware scheduling for periodic real-time tasks [J].
Aydin, H ;
Melhem, R ;
Mossé, D ;
Mejía-Alvarez, P .
IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (05) :584-600
[2]  
Borkar S, 2003, DES AUT CON, P338
[3]  
Brooks D, 2000, PROCEEDING OF THE 27TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P83, DOI [10.1145/342001.339657, 10.1109/ISCA.2000.854380]
[4]   A dynamic voltage scaled microprocessor system [J].
Burd, TD ;
Pering, TA ;
Stratakos, AJ ;
Brodersen, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) :1571-1580
[5]  
CHAPIRO DM, 1984, THESIS STANFORD U
[6]  
Chelcea T., 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era, P119, DOI 10.1109/IWV.2000.844540
[7]  
CHELCEA T, 2000, P DES AUT C, P21
[8]  
Chiou LY, 2003, DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, P96
[9]  
Culler DavidE., 1999, PARALLEL COMPUTER AR
[10]  
Deen MJ, 2003, PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, P697