Technological challenges of advanced CMOS processing and their impact on design aspects

The International Technology Roadmap for Semiconductors (ITRS) foresees the production of sub 10 nm gate length devices before 2016. To achieve this, both front- and back-end processing have to face major technological challenges and innovations. Lithography, device isolation, gate stack, shallow junctions, device engineering, high- and low-k dielectrics and interconnect schemes are hot research issues necessitating a global collaboration and the formation of appropriate platforms for joint research and development. Non-standard materials will have to be introduced and the use of nonclassical device architectures will be required. This paper reviews some of the on-going research efforts to come to cost effective solutions forming the backbone for future technology nodes. Special attention is given to the impact of these technological innovations on design aspects. An outlook is also given of the emerging technologies that are at the basis of the switch over from micro- to nanoelectronics.