Performance projections of scaled CMOS devices and circuits with strained Si-on-SiGe channels

Device and circuit simulations using a process/physics-based compact MOSFET model (UFPDB) are done to project the scaled CMOS speed-performance enhancement that can be expected from strained-Si channels on relaxed Si1-xGex buffer layers in bulk Si. With the UFPDB process-based parameters, associated With carrier mobility and velocity defined physically in,, terms of the Ge content x (0 less than or equal to x less than or equal to 0.50), and with threshold voltages (V-t) reduced due to the bandgap narrowing defined by x, but adjusted (for I-off control) to eilual those of the Si-channel control devices, UFPDB/Spice3 simulations of 60 nm CMOS. ring oscillators predict only a small speed enhancement when V-t is adjusted via channel doping. The peak enhancement is 5% for x 0.20. However, when a p(+) poly-SiGe gate is used to adjust V-t of the pMOSFET, A peak 16% speed enhancement at x = 0.30 is predicted; for pragmatic x = 0.26, the enhancement is 14%.