Ultra-shallow junction technology for 100 nm CMOS: xR LEAP implanter and RTP-centura rapid thermal annealer

被引：5

作者：

Current, MI

Lopes, D

Foad, M

Boyd, W

机构：

[1] Appl Mat Inc, Santa Clara, CA 95051 USA

[2] Appl Mat Inc, Horsham RH13 5PY, W Sussex, England

[3] Appl Mat Inc, Austin, TX 78754 USA

来源：

MATERIALS CHEMISTRY AND PHYSICS | 1998年 / 54卷 / 1-3期

关键词：

rapid thermal annealing; shallow junctions;

D O I：

10.1016/S0254-0584(98)00066-2

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Implantation of boron at sub-keV energies, combined with rapid thermal annealing in the temperature range from 900 to 1050 degrees C with soak times of 20 s or less results in activated junctions with depths of the order of 50 nm. These depths are consistent with roadmap estimates of transistor requirements for 100 nm scale devices for 16 Gb DRAM technology. (C) 1998 Elsevier Science S.A. All rights reserved.

引用

页码：33 / 36

页数：4

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