A monolithic digital clock-generator for on-chip clocking of custom DSP's

被引:24
作者
Nilsson, P
Torkelson, M
机构
[1] Department of Applied Electronics, University of Lund
[2] Lund Institute of Technology, Lund University, Lund
[3] Department of Applied Electronics, Lund University, Lund
[4] Lund University, Lund
[5] University of California, Berkeley, CA
[6] Ericsson Radio Systems, Stockholm
关键词
D O I
10.1109/4.509852
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work shows a robust and easily implemented clock generator for custom designs. It is a family digital design suitable fur both high-speed clocking and law-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 mu m standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage.
引用
收藏
页码:700 / 706
页数:7
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