Scaling constraints in nanoelectronic random-access memories

被引：72

作者：

Amsinck, CJ ^{[1
]}

Di Spigna, NH ^{[1
]}

Nackashi, DP ^{[1
]}

Franzon, PD ^{[1
]}

机构：

[1] N Carolina State Univ, Raleigh, NC 27695 USA

来源：

NANOTECHNOLOGY | 2005年 / 16卷 / 10期

关键词：

D O I：

10.1088/0957-4484/16/10/047

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.

引用

收藏

页码：2251 / 2260

页数：10

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