Multilevel nonvolatile memory effects in hybrid devices containing CdSe/ZnS nanoparticle double arrays embedded in the C60 matrices

被引：27

作者：

Li, Fushan ^{[1
]}

Cho, Sung Hwan ^{[1
]}

Son, Dong Ick ^{[1
]}

Park, Kyu Ha ^{[1
]}

Kim, Tae Whan ^{[1
]}

机构：

[1] Hanyang Univ, Div Elect & Comp Engn, Adv Semicond Res Ctr, Seoul 133791, South Korea

来源：

APPLIED PHYSICS LETTERS | 2008年 / 92卷 / 10期

关键词：

D O I：

10.1063/1.2898163

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Electrical properties of nonvolatile memory devices containing core/shell CdSe/ZnS nanoparticle double arrays embedded in the C-60 layers formed by using a spin-coating technique were investigated. Transmission electron microscopy images showed that CdSe/ZnS nanoparticles were randomly distributed in the C-60 layers. Capacitance-voltage (C-V) measurements on Al/C-60/double-stacked CdSe/ZnS nanoparticle arrays/C-60/p-Si devices showed that the flat-band voltage shift of the C-V curve related to the charge storage density was enhanced due to a stack of the CdSe/ZnS nanoparticle layers and that the flat-band voltage shift increased with the magnitude of applied bias voltage due to the variations of the charged electron density in the stacked CdSe/ZnS nanoparticle double arrays. (c) 2008 American Institute of Physics.

引用

页数：3

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