Upset hardened memory design for submicron CMOS technology

被引:832
作者
Calin, T [1 ]
Nicolaidis, M [1 ]
Velazco, R [1 ]
机构
[1] LSR,IMAG LAB,F-38031 GRENOBLE,FRANCE
关键词
D O I
10.1109/23.556880
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.
引用
收藏
页码:2874 / 2878
页数:5
相关论文
共 12 条
[1]   MEMORY SYSTEM-DESIGN FOR TOLERATING SINGLE EVENT UPSETS [J].
ABRAHAM, JA ;
DAVIDSON, ES ;
PATEL, JH .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1983, 30 (06) :4339-4344
[2]  
BESSOT D, P 1993 RADECS C, P563
[3]  
CALIN T, P 1995 INT TEST C, P45
[4]  
DRESSENDORFER TM, 1989, IONIZING RAD EFFECTS
[5]  
JOHNSON R, 1986, IEEE T NUCL SCI, V33, P1727
[6]  
KERNS SE, 1988, P IEEE NOV, P1470
[7]   LOW-POWER SEU IMMUNE CMOS MEMORY-CIRCUITS [J].
LIU, MN ;
WHITAKER, S .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1992, 39 (06) :1679-1684
[8]   CALCULATION OF COSMIC-RAY INDUCED SOFT UPSETS AND SCALING IN VLSI DEVICES [J].
PETERSEN, EL ;
SHAPIRO, P ;
ADAMS, JH ;
BURKE, EA .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1982, 29 (06) :2055-2063
[9]   AN SEU-HARDENED CMOS DATA LATCH DESIGN [J].
ROCKETT, LR .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1988, 35 (06) :1682-1687
[10]  
VELAZCO R, 1996, IEEE T NUCL SCI, V46