BSIM4 gate leakage model including source-drain partition

被引:115
作者
Cao, KM [1 ]
Lee, WC [1 ]
Liu, W [1 ]
Jin, X [1 ]
Su, P [1 ]
Fung, SKH [1 ]
An, JX [1 ]
Yu, B [1 ]
Hu, C [1 ]
机构
[1] Univ Calif Berkeley, Dept Elect & Comp Sci, Berkeley, CA 94720 USA
来源
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年
关键词
D O I
10.1109/IEDM.2000.904442
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Gate dielectric leakage current becomes a serious concern as sub-20 Angstrom gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.
引用
收藏
页码:815 / 818
页数:4
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