A low-parasitic collector construction for high-speed SiGe:C HBTs

被引:36
作者
Heinemann, B [1 ]
Barth, R [1 ]
Bolze, D [1 ]
Drews, J [1 ]
Formanek, P [1 ]
Grabolla, T [1 ]
Haak, U [1 ]
Höppner, W [1 ]
Knoll, D [1 ]
Köpke, K [1 ]
Kuck, B [1 ]
Kurps, R [1 ]
Marschmeyer, S [1 ]
Richter, HH [1 ]
Rücker, H [1 ]
Schley, P [1 ]
Schmidt, D [1 ]
Winkler, W [1 ]
Wolansky, D [1 ]
Wulf, HE [1 ]
Yamamoto, Y [1 ]
机构
[1] IHP, D-15236 Frankfurt, Oder, Germany
来源
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年
关键词
D O I
10.1109/IEDM.2004.1419123
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a new collector construction for high-speed SiGe:C HBTs that substantially reduces the parasitic base-collector capacitance by selectively underetching of the collector region. The impact of the collector module on RF performance is demonstrated in separate bipolar processes for npn and prip devices. A minimum gate delay of 3.2ps was achieved for CML ring oscillators with npn transistors featuring f(T)/ f(max) values of 300GHz/250GHz at BVCEO = 1.8V. For pnp devices with f(T)/ f(max) values of 135GHz /140GHz at BVCEO = 2.5V a gate delay of 5.9ps is demonstrated. Further vertical scaling of the doping profiles increases f(T) to 380GHz at BVCEO = 1.5V for npn's and 155GHz at BVCEO = 2.3V for pnp's, but ring oscillator speed and f(max), degraded.
引用
收藏
页码:251 / 254
页数:4
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