Electrical modeling of thin-film transistors

被引：75

作者：

Hong, D. ^{[1
]}

Yerubandi, G. ^{[1
]}

Chiang, H. Q. ^{[1
]}

Spiegelberg, M. C. ^{[1
]}

Wager, J. F. ^{[1
]}

机构：

[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA

来源：

CRITICAL REVIEWS IN SOLID STATE AND MATERIALS SCIENCES | 2008年 / 33卷 / 02期

关键词：

thin-film transistor; device modeling; square-law model; 3-layer model; comprehensive depletion-mode model; discrete trap model; conductance integral equation; channel mobility; fringing current artifacts; series resistance; trapping;

D O I：

10.1080/10408430701384808

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

An overview of device physics-oriented electrical modeling of thin-film transistors (TFTs) is presented. Four specific models are considered: (i) square-law, (ii) 3-layer, (iii) comprehensive depletion-mode, and (iv) discrete trap. For each model, a functional assessment of model equations is undertaken in terms of independent and dependent variables, model parameters, physical operating parameters, and constraining inequalities in order to facilitate mapping of model equations into a corresponding equivalent circuit. Channel mobility and "subthreshold" current trends are elucidated. Finally, a conductance integral equation based on Shockley's gradual channel approximation is introduced and is employed in model development and device assessment.

引用

页码：101 / 132

页数：32

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