A low-power SRAM design using quiet-bitline architecture

被引：6

作者：

Cheng, SP ^{[1
]}

Huang, SY ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Elect Engn Dept, Hsinchu, Taiwan

来源：

2005 IEEE International Workshop on Memory Technology, Design, and Testing - Proceedings | 2005年

关键词：

D O I：

10.1109/MTDT.2005.10

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a low-power SRAM design with quiet-bitline architecture by incorporating two major techniques. Firstly, we use a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. Secondly, we use a precharge-free pulling scheme for the read operation so as to keep all bitlines at low voltages at all times. SPICE simulation on a 2K-bit SRAM macro shows that such architecture can lead to a significant 84.4% power reduction over a self-designed baseline low-power SRAM macro.

引用

页码：135 / 139

页数：5

共 7 条

[1]

Benini L., 2001, IEEE Circuits and Systems Magazine, V1, P6, DOI 10.1109/7384.928306

[2] A 0.9V, 4K SRAM for embedded applications [J].