Low-power embedded SRAM with the current-mode write technique

In the traditional current-mode SRAM's, only the read operation is performed in the current mode, In this paper, we propose to use the current-mode technique tin both the read and write operations. Due to the current-mode operation, voltage swings at bit lines and data lines are kept very small during both read and write. Then, the ac power dissipation of bit lines and data lines, which is proportional to the voltage swing, can be significantly saved. A new current-mode 128 x 8 SEAM has been designed based on a 0.6-mu m CMOS technology, and the new SRAM consumes only 30% of the power of an SRAM with current-mode read but voltage-mode write operations. Besides a test chip for the new SRAM, it has also been embedded in an 8-bit mu-controller. Experimental results show good agreement with the simulation results and prove the feasibility of the new technique.