Quo Vadis nanoelectronics?

Semiconductor devices continue to be downscaled on a regular basis as technology provides the abitity to make smaller dimensions via improved lithography, a process which is known as Moore's Law. However, the driving force for the continued increase in number of devices on a chip is not this reduction in size, but the ability to put more functions on a chip with the same cost per unit area of Si. Nevertheless, it is not clear that our technology for Si devices can continue to work much longer. Here, I will discuss the driving forces, including energy dissipation, speed, area, and technological factors for the projected end-of-the roadmap technology. Yet, there continues to be a search for new device technologies to supplement, or replace, Si CMOS. Quantum wires have been sug-gested in many places as a possible new technology that can provide many opportunities for enhancing chip architecture. But, the constraints on any new technology can be viewed in terms of Si cost, and the manner in which new approaches to devices can be pursued will be dis-cussed. Some possible technologies are FinFETs, vertical quantum wires, carbon nanotubes, III-Vs, and similar ap-proaches. Device downsizing is: only one of three driving forces that lead to Moore's Law, with increasing chip size and circuit cleverness playing an equal part. This suggests that many novel devices should not be viewed as competition to CMOS, but in the light of how they may modify the circuit architecture. Indeed, circuit clev-erness has been as important in managing breakthroughs in the past as new processing technology. Some new op-portunities, that arise from the nature of nanowire fabrication, in these novel devices may lead to breakthroughs in the area of circuit cleverness. (C) 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.