Scaling analysis of multilevel interconnect temperatures for high-performance ICs

被引:145
作者
Im, S [1 ]
Srivastava, N
Banerjee, K
Goodson, KE
机构
[1] Stanford Univ, Dept Mat Sci, Stanford, CA 94305 USA
[2] Stanford Univ, Dept Engn & Mech Engn, Stanford, CA 94305 USA
[3] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA
关键词
electrothermal analysis; interconnects; Joule heating; low-K dielectrics; metal resistivity; size effect; temperature scaling; very large-scale integrated system (VLSI); via effect;
D O I
10.1109/TED.2005.859612
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a comprehensive thermal scaling analysis of multilevel interconnects in deep nanometer scale CMOS technologies based on technological, structural, and material data from the International Technology Roadmap for Semiconductors. Numerical simulations have been performed using three-dimensional electrothermal finite element methods, combined with accurate calculations of temperature- and size-dependent Cu resistivity and thermal conductivity of low-kappa interlayer dielectrics (ILD) based on fully physical models. The simulations also incorporate various scaling factors from fundamental material level to system level: the via-density-dependent effective ILD thermal conductivity, the hierarchically varying root mean square current stress based on SPICE simulations, and the thermal resistance of flip-chip package. It is shown that even after considering densely embedded vias, the interconnect temperature is expected to increase significantly with scaling, due to increasing current density, increasing surface and grain boundary contributions to metal resistivity, and decreasing ILD thermal conductivity.
引用
收藏
页码:2710 / 2719
页数:10
相关论文
共 34 条
[1]  
[Anonymous], 2001, P ASME INT MECH ENG
[2]  
Azzam R.M.A., 1977, Ellipsometry and Polarized Light
[3]  
Bakoglu H., 1990, CIRCUITS INTERCONNEC
[4]  
Banerjee K., 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), P885, DOI 10.1109/DAC.1999.782207
[5]   Global (interconnect) warming [J].
Banerjee, K ;
Mehrotra, A .
IEEE CIRCUITS & DEVICES, 2001, 17 (05) :16-32
[6]   Interconnect thermal modeling for accurate simulation of circuit timing and reliability [J].
Chen, DQ ;
Li, EH ;
Rosenbaum, E ;
Kang, SM .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (02) :197-205
[7]  
Cheng C., 2000, INTERCONNECT ANAL SY
[8]   Analytical thermal model for multilevel VLSI interconnects incorporating via effect [J].
Chiang, TY ;
Banerjee, K ;
Saraswat, KC .
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (01) :31-33
[9]   Thermal conductivity and sound velocities of hydrogen-silsesquioxane low-k dielectrics -: art. no. 094205 [J].
Costescu, RM ;
Bullen, AJ ;
Matamis, G ;
O'Hara, KE ;
Cahill, DG .
PHYSICAL REVIEW B, 2002, 65 (09) :942051-942056
[10]   Optical pump and probe measurement of the thermal conductivity of low-k dielectric thin films [J].
Daly, BC ;
Maris, HJ ;
Ford, WK ;
Antonelli, GA ;
Wong, L ;
Andideh, E .
JOURNAL OF APPLIED PHYSICS, 2002, 92 (10) :6005-6009