Room-temperature oxide field-effect transistor with buried channel

In this letter, we introduce an architecture for a room-temperature oxide channel field-effect transistor where the oxide channel material is buried below the gate oxide layer. This architecture has several significant advantages over the surface channel architecture [D. M. Newns, J. A. Misewich, C. C. Tseui, A. Gupta, B. A. Scott, and A. Schrott, Appl. Phys. Lett. 73, 780 (1998).] in coupling capacitance, channel mobility, and channel stability. Although the transconductance in the devices has been improved to 45 mu S (at V-d = 1 V and V-g = 2 V for a channel length of 1 mu m and width = 150 mu m), capacitance measurements show that the surface charge density is still below the optimal theoretical value. (C) 2000 American Institute of Physics. [S0003-6951(00)04724-0].