Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects

被引：3

作者：

Chen, K ^{[1
]}

Hu, CM ^{[1
]}

Fang, P ^{[1
]}

Lin, MR ^{[1
]}

Wollesen, DL ^{[1
]}

机构：

[1] ADV MICRO DEVICES INC, SUNNYVALE, CA 94088 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1997年 / 44卷 / 09期

关键词：

D O I：

10.1109/16.622616

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An experimentally confirmed accurate CMOS gate delay model is applied to the CMOS sing oscillators with interconnect loading. The optimum gate oxide thickness T-ox should he chosen differently as interconnect loading varies. Guidelines in choosing optimum T-ox for different interconnect Loading, combined with channel length and power supply scaling, are obtained.

引用

页码：1556 / 1558

页数：3

共 6 条

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Chen, K
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Chen, K
Hu, CM
Fang, P
Gupta, A
[J]. IEEE ELECTRON DEVICE LETTERS, 1997, 18 (06) : 275 - 277
[4] MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages
Chen, K
Wann, HC
Dunster, J
Ko, PK
Hu, CM
Yoshida, M
[J]. SOLID-STATE ELECTRONICS, 1996, 39 (10) : 1515 - 1518
[5] KUROI T, 1920, S VLSI
[6] OH SY, 1995, CIRCUITS DEVICES JAN

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